Sr. Systems Design Engineer

THE ROLE:

The CGCTools team develops and sustains the advanced debug infrastructure that underpins AMD's client, graphics, andcustomproduct lines. A CGCTools engineeris responsible forenabling endtoend debug capabilities spanning onchip instrumentation, JTAG over USBC solutions, automated data capture, and scalable serverside analysis. This role supports the full lifecycle of silicon: bringup, validation, customer debug, and highvolume production.

Key responsibilities include designing, implementing, andmaintainingtooling related to JTAG hardware, ADS (Automated Debug System), memory bringup, scan infrastructure, emerging technologies such asmicroprocessor baseddebug, and in-chassis hardware used to transport JTAG over USB. Engineers will collaborate crossfunctionally withAMD'sCSG Tools, S3 Platform, DFX/StimGen, validation teams, InfoSec, and external partners to deliver robust debug pathways both inside AMD labs and externally to ODMs and customers.

The role involves contributing to the development of nextgeneration debug architectures, enabling automated data collection pipelines,creatingor extending IP inspection libraries, and ensuring debug data is securely transported, preserved, andleveragedfor engineering analysis and AIbased tooling. CGCTools engineers support customerfacing debug workflows,participatein JTAG tool escalation processes, and develop firmware specifications for future silicon debug features. Workstreams also include shipping new external JTAG device software releases, supporting USBdriven scan,maintainingQA automation infrastructure, and enabling multiBU program readiness across upcoming SOCs.

THE PERSON:

Ideal candidates are systemsminded engineers with strong software, firmware, or hardware debugexpertise; familiarity with JTAG,Python, low level data manipulation, containerized tools, and largescale automation; and the ability to work across multiple SOC programs in a fastmoving environment. This role is central to the evolution of AMD's debug capability and requires technical depth, crossteam communication, and a passion for building reliable engineering infrastructure.

KEY RESPONSIBILITIES:

• Study upcoming SOCs andidentifyareas in need of advanced debug tools

• Work with IP teams toacquirefunctional understanding of IP blocks and procedures for making operational health assessments of the IP block's state

• Work with firmware teams to instrument debug data into mission mode firmware

• Work with IP teams to influence the addition of DFD features intofuturesilicon

• Write specs to outline how to perform debug data collection forin-chip microcontrollers responsible for executing debug actions

• Build Python libraries that can capture debug data and evaluate the health of an IP block

• Contributeto JTAG tools hardware development

• Contributeto JTAG tools softwaredevelopment

• Contribute to Automated Debug System debug service distributed application

• Build andmonitorautomated QA execution of debug toolssetup as CI/CD pipelines

• Assistin the construction of K8 containers to execute the debug service

• Work with regional Customer Engineering teams to enable AMD debug features withinendcustomer designs

• Work with IT and infosec to enable secure VPN tunnel for JTAG devices

PREFERRED EXPERIENCE:

• x86 system knowledge

• SOC internal architecture

• JTAG HW tools

• Python, C, Java,JavaScript

• Kubernetes containers

• Linux

• USB

• System level debugging

• BIOS

• Firmware development

• Platform design

• Validation knowledge

• Strong analytical/problem-solving skills and pronounced attention to details

• Must be a self-starter, and able to independently drive tasks to completion

• Debug techniques and methodologies

• Goodcommunicationskills

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegreeinElectrical Engineering, Computer Engineering,orComputerScience